Pseudoexhaustive BIST for sequential circuits

We present a method that can be used to test a sequential circuit pseudoexhaustively or almost pseudoexhaustively using LFSR/SRs as ATPGs with d-2^w test patterns, where d is the sequential depth and w is the input dependency limit. Our approach is based on the following techniques: (1) Use of LFSR/SRs as ATPGs (2) Rearrangement of the flip-flops of the circuit by retiming so that the hardware overhead for breaking all cycles and bounding the sequential depth is minimized. (3) Introduction of bypass storage cells (BSCs) so that no combinational element in the circuit has input dependence greater than a user-defined constant w. (4) Introduction of bypass delay cells (BDCs) so that the graph becomes more easily balanced or approximately balanced. Comparative experimental results indicate that our method behaves better than full-scan. It also outperforms a previous approach which, not only does not provide for on-chip TPG, but also requires O(q-f-2²) test patterns, where q is the total number of primary or pseudoprimary outputs in the circuit and f is the total number of flip-flops