Design for testability of asynchronous sequential circuits

Asynchronous sequential circuits are becoming increasingly important with their potential for higher speed and as clock skew problems in synchronous circuits continue to persist. Modifications to asynchronous machines that will allow ease of testability are presented in this paper. The framework of checking experiments is used for evaluating the proposed design. Checking experiments, though complex, can provide a methodology for complete functional testing as well as design verification. The design techniques proposed here can be adapted for testing under the traditional stuck-at fault model as well