Title :
Some results on the complexity of Boolean functions for table look up architectures
Author :
Murgai, Rajeev ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA, USA
Abstract :
We address the problem of determining the “complexity” of Boolean functions where complexity is measured as the minimum number of table look up blocks (TLUs) needed to implement a function. We present three new results. The first shows the exact value of the complexity of the class of (m+1)-input functions in terms of the TLUs with m inputs (m⩾2). The next two derive upper bounds on the complexity, given some information about the representation of the function. One bound needs the number of literals and the number of cubes in a sum-of-products representation, and the other, the number of literals in a factored form. We compare these bounds with the results obtained by a TLU synthesis tool. On average, the factored form bounds are about 20% higher than the synthesized results, and hence are reasonable predictors of the number of TLUs needed. This prediction capability can be employed to quickly estimate, without performing any technology mapping, if a circuit can fit on one chip
Keywords :
Boolean functions; computational complexity; table lookup; Boolean functions; TLU synthesis tool; complexity; table look up architectures; upper bounds; Boolean functions; Circuit synthesis; Contracts; Electronics packaging; Logic circuits; Logic functions; Programmable logic arrays; Upper bound;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393325