Title :
Heuristic minimization of synchronous relations
Author :
Singhal, Vigyan ; Watanabe, Yosinori ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Synchronous Boolean relations can represent sequential don´t-care information in synchronous systems. These relations allow greater flexibility in expressing don´t-care information than ordinary Boolean relations. Synchronous relations can be used to specify sequential designs at the finite state machine level as well as at the level of combinational elements and latches. The main objective of this paper is to present a heuristic approach to find a minimal implementation for a given synchronous relation. We also show that the synchronous relation formulation can also be used to find a minimal sum-of-products form which implements a function that is compatible with an arbitrary set of Boolean relations
Keywords :
Boolean functions; finite state machines; flip-flops; heuristic programming; logic design; minimisation; combinational elements; finite state machine; heuristic minimization; latches; minimal implementation; minimal sum-of-products form; sequential design specification; sequential don´t-care information; synchronous Boolean relations; Automata; Cost function; Design optimization; Field programmable gate arrays; Latches; Logic; Minimization; Sequential circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393339