Title :
Logic optimization with multi-output gates
Author :
Watanabe, Yosinori ; Guerra, Lisa ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
This paper is concerned with logic optimization of multi-output gates in multi-level combinational logic circuits. We address how a concurrent minimization over multiple gates can lead to further optimization as compared to conventional single-gate minimization techniques. In particular, we provide a procedure for computing a maximally-compatible set of permissible relations for multiple-output gates. We also propose a heuristic for clustering single-output gates into multi-output gates, so that increased concurrent optimization can be obtained
Keywords :
circuit optimisation; logic design; logic gates; minimisation; concurrent minimization; logic optimization; maximally-compatible set; multi-level combinational logic circuits; multi-output gates; permissible relations; single output gate clustering heuristic; Boolean functions; Combinational circuits; Contracts; Costs; Flexible printed circuits; Input variables; Logic circuits; Minimization; Programmable logic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393341
