Title :
A systolic architecture for high speed pipelined memories
Author :
Dickinson, A.G. ; Nicol, C.J.
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
Abstract :
Proposes a scalable memory architecture that maintains a high data rate, independent of address sequence and memory size. It is suitable for applications where throughput is of primary importance and access latency is tolerable. A rectangular array of memory blocks is pipelined to build a memory with an operating frequency determined only by the access time of a single block. This is independent of the number of blocks because address and data communication is localized to adjacent memory blocks. Rather than sacrificing speed for memory size, the new approach scales to provide high-throughput random access memories of very large size with some increase in latency
Keywords :
data communication; memory architecture; parallel architectures; pipeline processing; random-access storage; systolic arrays; RAM; access latency; access time; address sequence; data communication; high data rate; high speed pipelined memories; high-throughput random access memories; memory blocks; memory size; operating frequency; rectangular array; scalable memory architecture; systolic architecture; throughput; Data communication; Data structures; Databases; Decoding; Delay; Frequency; Pipeline processing; Random access memory; Throughput; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393343