Assembly and reliability of flip chips with a nano-filled wafer level underfill

The assembly and packaging of electronic devices today is becoming increasingly challenging and demanding because of requirements for smaller, faster and lighter products that provide increasing functionality at low cost. These requirements continue to place greater demands on the electronics industry and mandate improved packaging technology. In part, flip chip packaging technology is the response to these demands and provides a solution to these challenges. While flip chip packaging provides a solution to evolving device requirements, underfill materials are required to improve flip chip device reliability. These resins overcome poor device reliability issues resulting from the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. However, offsetting the gains in device reliability are additional processing steps that adversely affect manufacturing productivity. To compensate for this adverse effect on manufacturing productivity, several new processes, such as wafer level underfill, have been developed. In this paper, we describe the assembly and reliability of flip chips with a nanofilled wafer level underfill (WLU). This approach allows application of the underfill material on the entire wafer, such that many chips can be underfilled simultaneously. Assembly is then carried out with a compatible epoxy flux material. Air-to-air thermal shock (AATS) results and failure mechanisms are described for this novel approach