Highly-scalable 3D CLOS NOC for many-core CMPs

Author

Zia, Aamir ; Kannan, Sachhidh ; Rose, Garrett ; Chao, H. Jonathan

Author_Institution

Dept. of Electr. & Comput. Eng., Polytech. Inst. of NYU, Brooklyn, NY, USA

fYear

2010

fDate

20-23 June 2010

Firstpage

229

Lastpage

232

Abstract

In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.

Keywords

VLSI; low-power electronics; microprocessor chips; multistage interconnection networks; network topology; network-on-chip; power aware computing; 3D integrated CLOS network-on-chip; 3D mesh topology; high-performance interconnect infrastructure; highly-scalable 3D CLOS NOC; low-power interconnect infrastructure; many-core CMP; many-core chip multiprocessors; power consumption; processing elements; Network topology; Power demand; Power dissipation; Routing; Three dimensional displays; Topology; Wires; 3D IC; CLOS; VLSI; network-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

NEWCAS Conference (NEWCAS), 2010 8th IEEE International

Conference_Location

Montreal, QC

Print_ISBN

978-1-4244-6806-5

Electronic_ISBN

978-1-4244-6804-1

Type

conf

DOI

10.1109/NEWCAS.2010.5603776

Filename

5603776