The Application of Failure Analysis in Procuring and Screening of Integrated Circuits

The procedure for the testing, screening, and lot rejection of integrated circuits for the Apollo Guidance and Navigation Computer is described. The procedure, based on a knowledge of failure modes, failure mechanisms and contributing causes to failures in the manufacturing of devices, attempts to increase the reliability of integrated circuits. This is accomplished by screening and analyzing weak devices and using the generated data to quantitatively assess the lot for acceptance, rework or rejection. The technique, which is primarily aimed toward high-usage high-volume devices, was developed after extensive testing of many tens of thousands of integrated circuits. The process documents included in the appendix contain stress test procedures, classification of failure modes, numerical rejection limits per class of failure modes, internal visual rejection criteria, and leak test procedures. To emphasize the need for the described technique, data is presented showing variations among vendors and variation among procurement lots shipped from a single vendor. The contributing factors to the variations are discussed. A discussion of the evolution of the process documents is presented. The ultimate goal of the documents is the elimination or minimization of detected failure modes, Failure studies have shown that some failure modes are screenable with high confidence whereas attempts to screen other types of failure modes merely decrease the life of the device. In the later case, the detection durng short term stressing of devices which exhibit long time dependent failure modes is a low probability event.