Analog automatic test plan generator-Integrating with modular analog IC design environment

Analog automatic test plan generation (AATPG) was considered to be a difficult task until recently. We have developed a method to automate the test plan generation for analog ICs, which are designed using a modular design concept similar to that of digital ICs. However, it is still not clear exactly how this method can be put in the design and manufacturing process. Overall the automated test program generation process requires intricate knowledge of the design database of the chip, and the destination automatic test equipment (ATE), on which online testing of the ICs is to be performed. At the same time, it should be noted that consideration needs to be given to intermediate stages of extracting information from the design database, selection of appropriate method for test plan generation, test method specifications, test plan format, test plan to test program translator, optimization of the overall test plan and corresponding tester specific test program, deletion and addition of the tests, simulation of the entire test environment including device under test (DUT), extracting information of non-testable areas and, design alteration for higher test coverage. The article addresses the issues involved in each stage of the automatic test program generation process and explains how exactly it needs to be integrated with the design, manufacturing and testing process of analog ICs designed using newly emerging top-down modular design approach