Title :
A 350 µW 2.3 GHz integer-N frequency synthesizer for body area network applications
Author :
Masuch, Jens ; Delgado-Restituto, Manuel
Author_Institution :
Inst. of Microelectron. of Seville (IMSE-CNM-CSIC), Univ. of Seville, Seville, Spain
Abstract :
This paper presents a low power integer-N synthesizer with an output frequency of 2.3 GHz. The complete PLL has been integrated in a 90 nm CMOS technology and operates from a 1 V supply voltage. The synthesizer has been optimized for power consumption by employing an efficient quadrature VCO and a phase-switching prescaler. It achieves a phase noise of -121 dBc/Hz @3MHz while consuming only 350 μW in the PLL core. The typical reference spur level is about -40 dBc.
Keywords :
body area networks; frequency synthesizers; phase locked loops; power consumption; voltage-controlled oscillators; CMOS technology; PLL; body area network applications; frequency 2.3 GHz; integer-N frequency synthesizer; phase-switching prescaler; power 350 muW; power consumption; quadrature VCO; size 90 nm; voltage 1 V; Frequency measurement; Frequency synthesizers; Phase locked loops; Phase noise; Power demand; Synthesizers; Voltage-controlled oscillators;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-8060-9
DOI :
10.1109/SIRF.2011.5719342
