Title :
An efficient symbolic design verification system
Author :
Park, Jaehong ; Mercer, M. Ray
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Verifying the correctness of logic design has been an important problem for a long time. But there have been no efficient design verification tools for very large circuits. We present an efficient symbolic design verification method for very large circuits which exploits the properties of OPDDs (ordered partial decision diagrams). By symbolically extracting and simulating test patterns with OPDDs our design verification system provides time and space advantages over existing methods
Keywords :
decision theory; formal verification; logic CAD; logic design; OPDDs; correctness; design verification tools; efficient symbolic design verification system; logic design; ordered partial decision diagrams; symbolic design verification method; test patterns; very large circuits; Circuit simulation; Circuit testing; Combinational circuits; Contracts; Data structures; Design engineering; Design methodology; Logic circuits; Logic design; Manufacturing processes;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393363
