Title :
Illegal state extraction from Register Transfer Level
Author :
Hobeika, Christelle ; Thibeault, Claude ; Boland, Jean François
Author_Institution :
Electr. Eng. Dept., Ecole de Technol. Super., Montréal, QC, Canada
Abstract :
In this paper we present a new automated tool for illegal state identification at Register Transfer Level (RTL). This tool is the cornerstone of a new methodology for functional constraints extraction, to be applied in the ATPG process. Results show that our tool helps reducing overtesting and false error detection during verification.
Keywords :
VLSI; automatic test pattern generation; ATPG process; automated test pattern generation; false error detection; functional constraint extraction; illegal state extraction; register transfer level; Automatic test pattern generation; Circuit faults; Computer architecture; Delay; Hardware design languages; Radiation detectors;
Conference_Titel :
NEWCAS Conference (NEWCAS), 2010 8th IEEE International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-6806-5
Electronic_ISBN :
978-1-4244-6804-1
DOI :
10.1109/NEWCAS.2010.5603786
