Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach

In this paper, we present a novel bit-parallel systolic multiplier for the shifted dual basis of GF(2^m). It is demonstrated that the shifted dual basis multiplication for trinomials can be represented by the sum of two Hankel matrix-vector multiplications. Thus, the proposed bit-parallel systolic multiplier is composed of one Hankel multiplier and one (2m-1)-bit adder. Moreover, we use the algebraic encoding scheme of the cyclic code to implement the multiplications with concurrent error detection. It is analytically shown that the latency overhead is extra two clock cycles as compared to the multiplier without concurrent error detection. In the binary field GF(2²³³), the space overhead of the proposed architecture using cyclic code is about 7.2%.