Title :
Synthesis of controllers from interval temporal logic specification
Author :
Fujita, Masahiro ; Kono, Shinji
Author_Institution :
Fujitsu Lab. Ltd., Kawasaki, Japan
Abstract :
Presents a method which accepts interval temporal logic (ITL) formulas as a specification and automatically generates state machines. The specification in ITL can also be used as a constraint for a state machine that is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further processed by a logic synthesizer, such as SIS. We present experimental results and show the usefulness of our method
Keywords :
control system synthesis; controllers; formal specification; logic CAD; microcontrollers; sequential circuits; systems re-engineering; temporal logic; SIS; automatic state machine generation; change engineering; constraint; controller synthesis; interval temporal logic specification; logic synthesizer; redesign; sequential circuit; Automatic control; Automatic logic units; Binary decision diagrams; Circuit synthesis; Clocks; Digital circuits; Logic circuits; Logic programming; Sequential circuits; Synthesizers;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393373
