Title :
A C-testable carry-free divider
Author :
Srinivas, H.R. ; Vinnakota, B. ; Parhi, Keshab K.
Abstract :
The design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and modified to make it C-testable, i.e. it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers that used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two´s-complement form is shown not to be C-testable. It is modified to be linear-testable (in word-length), instead of taking the exponential time required for exhaustively testing all possible combinations at its inputs
Keywords :
Arithmetic; Encoding; Hardware; Logic arrays; Logic devices; Logic gates; Logic testing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393379