A 8.8-ns 54×54-bit multiplier using new redundant binary architecture

Author

Makino, Hiroshi ; Nakase, Yasunobu ; Shinohara, Hirofumi

Author_Institution

Mitsubishi Electr. Corp., Mizuhara, Itami, Japan

fYear

1993

fDate

3-6 Oct 1993

Firstpage

202

Lastpage

205

Abstract

A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuitry or latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry-propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. A multiplication time of 8.8 ns is obtained by SPICE2 simulation for a supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers

Keywords

CMOS integrated circuits; SPICE; adders; data conversion; multiplying circuits; redundancy; 0.5 micron; 0.9 s; 3.3 V; 54 bit; 8.8 ns; CMOS technology; SPICE2 simulation; Wallace tree; binary number convertor; carry-propagation circuit; latency; multiplication time; multiplier; normal binary number; partial products; redundant binary adders; redundant binary architecture; selector circuits; supply voltage; Adders; CMOS technology; Circuit simulation; Compressors; Delay; Integrated circuit interconnections; Laboratories; Large scale integration; Niobium; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393380

Filename

393380