A 400 MHz wave-pipelined 8×8-bit multiplier in CMOS technology

We attempt to exploit wave pipelining in CMOS technology. We use Normal Process Complementary Pass Transistor Logic (NPCPL) which is modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8-bit multiplier is designed using this logic in a 0.8 μ technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.8 W. The methodology can be extended to introduce wave pipelining in other circuits as well