Title :
Fault-tolerant content addressable memory
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
Abstract :
We analyze the error behavior of content addressable memories and provide necessary and sufficient conditions to protect them. Single error tolerant designs are demonstrated for bit- and byte-organized content addressable memories. This level of protection is equivalent to that of the conventional ECC protection in memory subsystems
Keywords :
content-addressable storage; error analysis; fault tolerant computing; memory architecture; ECC protection; content addressable memories; error behavior; error tolerant designs; fault tolerant content addressable memory; memory subsystems; Associative memory; CADCAM; Circuit faults; Computer aided manufacturing; Error correction codes; Fault tolerance; Logic; Protection; Random access memory; Read-write memory;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393382
