SMAC: A scene matching chip

Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching is a technique for reducing the amount of computation involved in scene matching applications. Most of the past research on this problem has concentrated on efficient software algorithms, and very little effort has been expended on custom hardware solutions. We describe the design of SMAC, a new VLSI architecture for Hierarchical Scene Matching. This architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. The paper also describes the design and implementation of a prototype CMOS VLSI chip that implements the exhaustive search task of the scene matching algorithm