A comparison of synchronous and asynchronous FSMD designs

Author

Auletta, Richard ; Reese, Bob ; Traver, Cherrice

Author_Institution

Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

178

Lastpage

182

Abstract

This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs. The comparison is made through independent parallel designs of a 16-bit factoring ASIC. A common functional specification, standard cell library, and suite of EDA tools for layout and simulation are used to provide a common basis for comparison. To clarify design goals and provide more data for comparison each design is separately optimized for speed and for area. Timing and area information for each design is tabulated and discussed to illustrate the specific advantages and disadvantages of each approach

Keywords

application specific integrated circuits; circuit CAD; circuit analysis computing; finite state machines; EDA tools; area information; asynchronous FSMD; data path ASIC; factoring ASIC; finite state machine; functional specification; layout; parallel designs; simulation; standard cell implementations; standard cell library; synchronous FSMD; timing; Application specific integrated circuits; Asynchronous circuits; Clocks; Data engineering; Delay estimation; Design optimization; Electronic design automation and methodology; Integrated circuit interconnections; Libraries; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393385

Filename

393385