Title :
Tracking radar digital matched-filter ASIC design and its error analysis
Author :
Zhou, Zhenyu Liu Zhimei ; Yueqiu Han
Author_Institution :
Dept. of Electron. Eng., Beijing Inst. of Technol., China
Abstract :
The matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of a digital tracking radar matched-filter, whose hardware overhead is one third of the traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is highly improved. The whole digital matched-filter is implemented in just one FPGA chip. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signals in 102 μs. The signal-to-noise ratio formula of this matched-filter is deduced at the end of the paper.
Keywords :
application specific integrated circuits; backscatter; digital filters; error analysis; field programmable gate arrays; floating point arithmetic; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; matched filters; pulse compression; radar signal processing; radar tracking; tracking filters; 102 mus; ASIC work modes; FPGA; SNR; block-floating-point arithmetic; filter error analysis; processing throughput/precision; pulse compression; radar backscattering signal processing; real time signal processing; signal-to-noise ratio; tracking radar digital matched-filter ASIC design; Application specific integrated circuits; Arithmetic; Error analysis; Field programmable gate arrays; Hardware; Pulse compression methods; Radar signal processing; Radar tracking; Signal to noise ratio; Throughput;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1115039
