DocumentCode :
260
Title :
T-SPaCS—A Two-Level Single-Pass Cache Simulation Methodology
Author :
Zang, Wei ; Gordon-Ross, Ann
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
Volume :
62
Issue :
2
fYear :
2013
fDate :
Feb. 2013
Firstpage :
390
Lastpage :
403
Abstract :
The cache hierarchy´s large contribution to total microprocessor system power makes caches a good optimization candidate. To facilitate a fast design-time cache optimization process, we propose a single-pass trace-driven cache simulation methodology-T-SPaCS-for a two-level exclusive cache hierarchy. Direct adaptation of conventional trace-driven cache simulation to two-level caches requires significant storage and simulation time as numerous stacks record cache access patterns for each level one and level two cache combination and each stack is repeatedly processed. T-SPaCS significantly reduces storage space and simulation time using a set of stacks that only record the complete cache access pattern. Thereby, T-SPaCS simulates all cache configurations for both the level one and level two caches simultaneously in a single pass. Experimental results show that T-SPaCS is 21.02X faster on average than sequential simulation for instruction caches and 33.34X faster for data caches. A simplified, but minimally lossy version of T-SPaCS (simplified-T-SPaCS) increases the average simulation speedup to 30.15X for instruction caches and 41.31X for data caches. We leverage T-SPaCS and simplified-T-SPaCS for determining the lowest energy cache configuration to quantify the effects of lossiness and observe that T-SPaCS and simplified-T-SPaCS still find the lowest energy cache configuration as compared to exact simulation.
Keywords :
cache storage; T-SPaCS; cache hierarchy; design-time cache optimization process; energy cache configuration; microprocessor system power; single-pass trace-driven cache simulation; stacks record cache access pattern; storage space; two-level single-pass cache simulation; Algorithm design and analysis; Analytical models; Complexity theory; Computational modeling; Data models; Program processors; Tuning; Cache memories; low-power design; real-time systems and embedded systems; simulation;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2011.194
Filename :
6035684
Link To Document :
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