DocumentCode :
2600033
Title :
Design for standard impact pulses of drop tester using dynamic simulation
Author :
Ng, Hun Shen ; Tee, Tong Yan ; Luan, Jing-En
Author_Institution :
STMicroelectronics, Singapore, Singapore
fYear :
2004
fDate :
8-10 Dec. 2004
Firstpage :
793
Lastpage :
799
Abstract :
Board level solder joint reliability during drop impact is a great concern to semiconductor and electronic product manufacturers, especially for handheld or portable telecommunication devices. A new JEDEC standard for board level drop test of handheld electronic products was released to specify the drop test procedure and conditions. The standard recommends a specific input shock pulse to the PCB subassembly. However, the impact pulse is a complex function of various drop tester design parameters such as the drop block, absorbing material, strike surface materials and dimensions, as well as different testing conditions such as drop height. Therefore, many time-consuming experimental trial-and-errors are required to calibrate and characterize a drop tester to achieve the required impact pulse before actual drop testing can be performed. Thus, dynamic simulation using free-fall drop model is a useful tool to provide design guidelines to achieve the required impact pulse, and to shorten the drop tester characterization process considerably. It is found that the peak acceleration and pulse duration of the impact pulse are strongly affected by the drop block density and thickness as well as absorbing surface modulus and thickness. The drop height affects the peak acceleration but is insignificant on the pulse duration. An empirical relationship is developed to determine the different designs parameters on the peak acceleration and pulse duration. However, in a drop tester, the drop block and the strike surface are usually design constraints. The design parameters that can be varied to achieve the desired impact pulse are the absorbing material and dimensions as well as the drop height. Therefore, a design flowchart is developed to calibrate and characterize the drop tester to achieve the desired impact pulse. The settings of impact pulses for various JEDEC levels A to G are then determined numerically, which are useful references for drop testing engineers.
Keywords :
impact testing; integrated circuit packaging; integrated circuit reliability; printed circuit manufacture; JEDEC standard; PCB subassembly; board level drop test; board level solder joint reliability; drop impact; drop test conditions; drop test procedure; drop tester characterization process; dynamic simulation; free-fall drop model; handheld electronic products; standard impact pulses; telecommunication devices; Acceleration; Electric shock; Electronic equipment testing; Flowcharts; Guidelines; Materials testing; Performance evaluation; Semiconductor device manufacture; Semiconductor device reliability; Soldering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
Print_ISBN :
0-7803-8821-6
Type :
conf
DOI :
10.1109/EPTC.2004.1396717
Filename :
1396717
Link To Document :
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