A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS

Author

Mizuno, H. ; Miyazaki, M. ; Ishibashi, K. ; Nakagome, Y. ; Nagano, T.

Author_Institution

Central Research Laboratory, Hitachi, Ltd. Kokubunji, Tokyo 185, Japan

fYear

1997

fDate

12-14 June 1997

Firstpage

Lastpage

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-76-X

Type

DOI

10.1109/VLSIC.1997.623824

Filename

623824

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