All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs

Author

Gotoh, K. ; Wakayama, S. ; Saito, M. ; Ogawa, J. ; Tamura, H. ; Okajima, Y. ; Taguchi, M.

Author_Institution

Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan

fYear

1997

fDate

12-14 June 1997

Firstpage

107

Lastpage

108

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-76-X

Type

DOI

10.1109/VLSIC.1997.623830

Filename

623830

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