Title :
All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs
Author :
Gotoh, K. ; Wakayama, S. ; Saito, M. ; Ogawa, J. ; Tamura, H. ; Okajima, Y. ; Taguchi, M.
Author_Institution :
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
Conference_Titel :
VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-76-X
DOI :
10.1109/VLSIC.1997.623830
