About set and skewed associativity on second-level caches

In order to achieve high performance on high-end microprocessor systems, second level caches are associated with the microprocessors. Most of current second-level caches are direct-mapped. Recently, a new organization of a partially associative cache was proposed: the skewed-associative cache. In this paper, we investigate the use of partially associative organizations for second-level caches. When the second-level cache lags are implemented on the same chip as the cache controller, the data array in the second-level cache may be organized as a single cache bank and then may be as simple as in the direct-mapped case. Three driven simulations were conducted. They show that using some degree of associativity, and particularly skewed-associativity, on the second-level cache is particularly worthwhile because it significantly reduces both execution time and memory traffic