A split data cache for superscalar processors

Superscalar implementations of RISC architectures are emerging as the dominant high-performance microprocessor technology for the mid-1990´s. This paper proposes and evaluates a split data cache memory design, a new memory system ehancement for superscalar processor architectures. This design allows floating-point and integer memory access to be executed in parallel. The configuration is well matched to the dual-path execution hardware of many current superscalar processors. It doubles peak bandwidth without the expense or complexity of multi-ported memory, and increases the processor´s ability to exploit fine-grained parallelism. The reported simulation results show that by using this enhancement, a speedup of more than 1.5 over the traditional unified cache model can be achieved on some standard benchmarks. The speedup is not uniform among all programs. Several hypotheses are presented and experimentally validated to explain these results