• DocumentCode
    2600353
  • Title

    A recursive technique for computing lower-bound performance of schedules

  • Author

    Langevin, Michel ; Cerny, Eduard

  • Author_Institution
    Dep. d´´IRO, Montreal Univ., Que., Canada
  • fYear
    1993
  • fDate
    3-6 Oct 1993
  • Firstpage
    16
  • Lastpage
    20
  • Abstract
    Presents a fast recursive technique for estimating a lower-bound performance of data path schedules. The method relies on the determination of an ASAPUC (as soon as possible under constraint) time-step value for the root of the DFG (data flow graph) that is based on the ASAPUC values of its predecessor nodes, etc., until the leaf nodes are reached where this value becomes the regular ASAP value. The method computes a tighter lower-bound than the greedy technique and is only two times slower on the same benchmarks. Synthesis methods that depend on the exploration of the solution space directed by a lower-bound estimation, such a local microcode generation and behavioral synthesis, can benefit from our method. This is because bad solutions can be pruned earlier. We illustrate this dramatic effect on the reduction of the search space during the synthesis of an optimal microcode sequence for the elliptic wave filter benchmark and a fixed data path (containing a multiport RAM and a ROM)
  • Keywords
    data flow graphs; digital filters; elliptic filters; firmware; high level synthesis; performance evaluation; scheduling; search problems; ASAPUC time step; ROM; as soon as possible under constraint; bad solution pruning; behavioral synthesis; data flow graph; data path schedules; elliptic wave filter benchmark; greedy technique; leaf nodes; local microcode generation; lower-bound estimation; lower-bound performance; multiport RAM; optimal microcode sequence; predecessor nodes; recursive technique; search space reduction; solution space exploration; Filters; Flow graphs; Greedy algorithms; Integer linear programming; Optimal control; Processor scheduling; Read only memory; Relaxation methods; Scheduling algorithm; Space exploration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-4230-0
  • Type

    conf

  • DOI
    10.1109/ICCD.1993.393412
  • Filename
    393412