DocumentCode :
2601001
Title :
Reducing power consumption of instruction ROMs by exploiting instruction frequency
Author :
Inoue, Koji ; Moshnyaga, Vasily G. ; Murakami, Kazuaki
Author_Institution :
Dept. of Electron. Eng.& Comput. Sci., Fukuoka Univ., Japan
Volume :
2
fYear :
2002
fDate :
2002
Firstpage :
1
Abstract :
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates ´0´, the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many ´1´s´ are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.
Keywords :
embedded systems; integrated memory circuits; low-power electronics; read-only storage; switching; application programs analysis; binary-patterns; bit-line switching activity; bit-line switching reduction; embedded systems; instruction ROMs; instruction frequency; low power ROMs; op-codes; power consumption reduction; Batteries; Computer science; Embedded system; Energy consumption; Frequency; Informatics; Pattern analysis; Random access memory; Read only memory; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
Type :
conf
DOI :
10.1109/APCCAS.2002.1115094
Filename :
1115094
Link To Document :
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