Bit-level retiming of high-speed digital recursive filters

In pipelining recursive digital filters, the benefits of additional extra registers to reduce the critical path of arithmetic blocks competes with the decrease of throughput due to extra signal delays in the filter cycle. It is shown in this paper that the problem can be avoided by judicious placement of the registers in the critical recursive loop at the bit level. This is akin to re-timing of signal flow graphs. Unit delay models of direct-form recursive filters and 2^nd order allpass IIRs are studied. Bit-level retiming is shown to decrease the critical path delay by a factor of 2.5 in the best case. The performances of the pre- and post-layout design examples are compared with the results confirming the effectiveness of the retiming scheme.