Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

Author

Saitoh, Motofumi ; Ogura, Takashi ; Masuzaki, Koji ; Takahashi, Kensuke ; Sunamura, Hiroshi ; Manabe, Kenzo ; Shirai, Hiroki ; Tatsumi, Toru ; Watanabe, Hirohito

Author_Institution

NEC Corp., Sagamihara

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

69

Lastpage

72

Abstract

Fabrication process of phase controlled FUSI (PC-FUSI)/HfSiON gate structure for small SRAM cells formation is proposed. The critical issue is controlled NiSi/Ni₃Si boundary formation between the N-FET and P-FET gate electrode within a narrow STI region with wide process margin. This was realized by adopting a hard mask process to selectively form N/P-FET FUSI under tuned sintering condition. Suitable V_th for LSTP devices, +/-0.45 V, and good transistor performance, I_on=550/310 muA/mum at I_off=20 pA/mum, were obtained with L_g=55 nm. Operation of 0.446 mum² SRAM cells was confirmed even at 0.8 V with a static noise margin of 181 mV. We also discuss suitability of a PC-FUSI/HfSiON gate for embedded DRAM cell transistors.

Keywords

CMOS memory circuits; DRAM chips; SRAM chips; hafnium compounds; nickel compounds; HfSiON; LSTP CMOS platform; LSTP devices; N-FET gate electrode; NiSi-Ni₃Si; P-FET gate electrode; PC-FUSI-HfSiON gate structure; SRAM cells formation; embedded DRAM cell transistors; embedded memory application; hard mask process; integration technology; phase controlled FUSI fabrication process; static noise; tuned sintering condition; voltage 0.8 V; voltage 181 mV; Annealing; CMOSFETs; Dry etching; Electrodes; Fabrication; Insulation; Laboratories; National electric code; Random access memory; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418865

Filename

4418865