Use of Test Patterns in Evaluating the Reliability of Integrated Circuits

The reliability of a large scale integrated circuit chip is an aggregate of the reliability of each of its constituents. Therefore, the total failure rate is determined by simply evaluating the contribution of each constituent individually and independently. This is achieved by subjecting each part (e.g. a devrice or a conductor) to stress testing and subsequently translating its failure rate to machine-use conditions. Such tests, however, cannot be performed on a complex product chip because it is impossible to isolate a desired area. The only answer to this problem is to design a test pattern for each of the necessary tests. To illustrate the effectiveness of this vehicle, a special test chip designed to evaluate the reliability of Cogar´s high performance read-write memory system is described in detail.