DocumentCode :
2602027
Title :
On the Performance Limit of Impact-Ionization Transistors
Author :
Shen, C. ; Lin, J.Q. ; Toh, E.-H. ; Chang, K.-F. ; Bai, P. ; Heng, C.H. ; Samudra, G.S. ; Yeo, Y.C.
Author_Institution :
Nat. Univ. of Singapore, Singapore
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
117
Lastpage :
120
Abstract :
The trade-off between off-state leakage current and switching delay for impact-ionization MOS transistor (I-MOS) is pointed out and studied for the first time. This trade-off is unique for I-MOS devices, and is related to the self-amplifying carrier multiplication, the exact phenomenon used to be viewed as a merit. Monte-Carlo simulation is performed to study the random process of carrier multiplication in I-MOS, and the physical limit to the transistor switching delay is assessed. We found that at leakage constraints of 0.1muA/mum, silicon I-MOS shows long intrinsic switch-on delay (>10ps) and large random delay variance, hence does not show advantage in the delay/leakage trade-off compared to CMOS devices.
Keywords :
MOSFET; Monte Carlo methods; leakage currents; random processes; silicon; I-MOS devices; Monte Carlo simulation; Si; impact-ionization MOS transistor; off-state leakage current; random process; self-amplifying carrier multiplication; transistor switching delay; CMOS technology; Delay; High performance computing; Impact ionization; Leakage current; MOSFETs; Physics; Silicon; Stochastic processes; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
Type :
conf
DOI :
10.1109/IEDM.2007.4418878
Filename :
4418878
Link To Document :
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