Analytical delay variation modeling for evaluating sub-threshold synchronous/asynchronous designs

Digital Sub-threshold circuits are highly susceptible to large delay variations due to Process, Voltage and Temperature (PVT) variations, hence compromising their operation robustness. In this paper, we propose and analytically derive the delay variation models of digital sub-threshold circuits with PVT variations, and verify the models through computer simulations (@ 130nm CMOS BSIM4 HSPICE model). We show that, on average, the delay variation (due to PVT) can be up to 3.2×, and the modeling error of our proposed m odels is 8%. We further compare, by means of Adder circuits, th e synchronous approach (with safety timing margins applied) against the asynchronous Quasi Delay Insensitive (QDI) approach (with self-detected completion circuits). We show that the synchronous design is less competitive in terms of speed and energy when the delay margins are more than 0.7× and 2.9× respectively. We show that QDI approach is most appropriate for sub-threshold operation when the delay variations are large.