Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs

We report a new silicon-germanium-tin (SiGeSn) source and drain stressor with large lattice-mismatch with respect to Si or SiGe for channel strain engineering, and its integration in a SiGe-channel p-FET for performance enhancement. A novel CMOS-compatible process was developed to incorporate Sn in SiGe S/D with high levels of Sn-substitutionality: Sn implant into Si_0.75Ge_0.25 source and drain (S/D) regions, followed by either excimer laser annealing (LA) or solid phase epitaxy (SPE) to restore S/D crystallinity. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 8% in SiGe S/D regions, equivalent to forming Si_0.4Ge_0.6 in the S/D region, enhancement of I_Dsat and hole mobility are 82% and 135%, respectively, over control p- FETs without Sn incorporation. With the first demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FFT enhancement.