VLSI selftest as a `layer´ of built-in test-a case study

The testability problem for VLSI circuits is discussed. Guidelines for the inclusion of custom VLSI testability features into the built-in test (BIT) mechanization of an electronic systems design are presented along with some lessons learned from its actual incorporation into a completed electronics system. It is concluded that the impacts on cost and schedule resulting from a deficiency of VLSI testability features in the typical design process can be significantly reduced by the proper implementation of a VLSI layer of BIT fully integrated with the remaining BIT functional tests. Some of the benefits are outlined