Title :
Design and VHDL modeling of all-digital PLLs
Author :
Zianbetov, E. ; Javidan, M. ; Anceau, F. ; Galayko, D. ; Colinet, E. ; Juillard, J.
Author_Institution :
LIP6 Lab., Paris VI Univ., Paris, France
Abstract :
In this paper, a VHDL model of a second-order all-digital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistor-level model.
Keywords :
clocks; digital phase locked loops; hardware description languages; phase detectors; VHDL modeling; asynchronous operation; bang-bang phase detectors; digital multi-bit phase-frequency detector; distributed clock generators; metastability issues; second-order all-digital phase-locked loop; transistor-level model; Clocks; Delay; Latches; Phase frequency detector; Phase locked loops; Semiconductor device modeling; Synchronization;
Conference_Titel :
NEWCAS Conference (NEWCAS), 2010 8th IEEE International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-6806-5
Electronic_ISBN :
978-1-4244-6804-1
DOI :
10.1109/NEWCAS.2010.5603947