DocumentCode :
2602625
Title :
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL
Author :
Reas, Rosario M. ; Alvarez, Anastacia B. ; Reyes, Joy Alinda P
Author_Institution :
Intel Microprocessors Lab., Univ. of the Philippines, Quezon City, Philippines
fYear :
2010
fDate :
24-26 March 2010
Firstpage :
153
Lastpage :
158
Abstract :
Improving the performance of on-chip caches has been continually regarded with much effort to provide solution to the increased performance gap between microprocessor and memory. Proposed new design techniques were mostly implemented in software simply because it is easier and faster than hardware implementation. However, with the microprocessor technology advancement, this approach fails to consider other crucial matters such as power and area. To investigate and further evaluate the dynamic partitioning schemes in a shared L2 cache in Chip Multiprocessors (CMP), we have come up with a model to bring together generated traces from the M5 simulator and the hardware implementation of a shared L2 cache described using Verilog Hardware Description Language (HDL) and developed using the Synopsys EDA tools. The use of this system model offers a number of benefits such as the following: (1) L2 cache designs can now be characterized using power and area measurements and not just performance gain alone, (2) processor and L1 caches can be abstracted away from the design to provide more focus, (3) standard benchmark can still be used to evaluate the different designs being compared, and (4) a more realistic design that is closer to getting materialized can be produced.
Keywords :
cache storage; hardware description languages; logic partitioning; microprocessor chips; multiprocessing systems; Hardware Description Language; L1 caches; M5 simulator; Synopsys EDA tools; Verilog HDL; dynamic partitioning schemes; multiprocessor chip; on-chip cache performance; shared L2 cache; standard benchmark simulation; chip multiprocessors; dynamic cache partitioning schemes; hardware description language (hdl); shared L2 cache;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Modelling and Simulation (UKSim), 2010 12th International Conference on
Conference_Location :
Cambridge
Print_ISBN :
978-1-4244-6614-6
Type :
conf
DOI :
10.1109/UKSIM.2010.35
Filename :
5481047
Link To Document :
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