Experiences in simulating a declarative multiprocessor

There has been extensive research into nonconventional, non-von Neumann parallel computer architectures and declarative programming languages. Dataflow and reduction multiprocessors are examples of such machines which exhibit novel architectures. The Flagship parallel reduction machine is one such multiprocessor using a packet-based graph reduction model of computation to exploit the parallelism inherent in functional languages. A functional simulator for the Flagship machine has been written for studying the functional characteristics of the machine. However, the functional simulator only simulates the actions of the executional units, with no notion of the time involved. For performance evaluation, timing characteristics must be monitored. This paper describes a technique for introducing an event-driven timing scheme into the functional simulator. With the introduction of such a scheme, certain synchronisation issues arise due to the functionality of the simulator. This paper also describes ways of resolving these issues. The architecture is MIMD, based on a set of tightly-coupled processor-store pairs interconnected by a delta network. This is a commonly used architecture, so anyone intending to simulate a similar architecture can draw from the experiences as related in this paper