Title : 
High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology
         
        
            Author : 
Miyashita, Tadakazu ; Ikeda, Ken-ichi ; Kim, Yong Sin ; Yamamoto, Takayuki ; Sambonsugi, Y. ; Ochimizu, H. ; Sakoda, Tatsuya ; Okuno, Masayuki ; Minakata, Hideaki ; Ohta, Hitoyoshi ; Hayami, Y. ; Ookoshi, K. ; Shimamune, Y. ; Fukuda, Motohisa ; Hatada, Ak
         
        
            Author_Institution : 
Fujitsu Lab. Ltd., Tokyo
         
        
        
        
        
        
            Abstract : 
We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.
         
        
            Keywords : 
CMOS logic circuits; CMOS memory circuits; MOSFET; SRAM chips; integrated circuit interconnections; low-k dielectric thin films; BEOL integration; FET specific multiple-stressors; NFET drive currents; PFET drive currents; RC delay; full-porous low-k interconnects; functional high density SRAM; high-epsilon offset spacer; low-power bulk CMOS platform technology; size 45 nm; total circuit delay; ultra low-k BEOL technology; CMOS logic circuits; CMOS technology; Capacitive sensors; Delay; FETs; Integrated circuit interconnections; Large-scale systems; Random access memory; Space technology; Wiring;
         
        
        
        
            Conference_Titel : 
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
         
        
            Conference_Location : 
Washington, DC
         
        
            Print_ISBN : 
978-1-4244-1507-6
         
        
            Electronic_ISBN : 
978-1-4244-1508-3
         
        
        
            DOI : 
10.1109/IEDM.2007.4418915