Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

Author

Trivedi, Amit Ranjan ; Yueh, Wen ; Mukhopadhyay, Saibal

Author_Institution

Dept. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

23-26 Oct. 2011

Firstpage

105

Lastpage

108

Abstract

We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.

Keywords

capacitance; three-dimensional integrated circuits; 3D-Stacks; P-G TSV; frequency dependent capacitance; high frequency supply noise; high-frequency PDN impedance; on-chip distributed decoupling capacitance; power delivery network; power-ground through-silicon-via; through-silicon-via capacitance; Capacitance; Frequency dependence; Impedance; Noise; Substrates; Three dimensional displays; Through-silicon vias; 3DIC; High frequency noise; Power Delivery Network; Through-Silicon-Via;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on

Conference_Location

San Jose, CA

ISSN

pending

Print_ISBN

978-1-4244-9398-2

Electronic_ISBN

pending

Type

conf

DOI

10.1109/EPEPS.2011.6100199

Filename

6100199