DocumentCode :
2602849
Title :
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
Author :
Shien-Yang Wu ; Chou, C.W. ; Lin, Colin Yu ; Chiang, M.C. ; Yang, Chih-Kong Ken ; Liu, M.Y. ; Hu, L.C. ; Chang, C. Hwa ; Wu, P.H. ; Chen, H.F. ; Chang, S.Y. ; Wang, S.H. ; Tong, P.Y. ; Hsieh, Y.L. ; Liaw, J.J. ; Pan, K.H. ; Hsieh, C.H. ; Chen, C.H. ; Chen
Author_Institution :
Taiwan Semicond. Manuf. Co., Hsin-Chu
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
263
Lastpage :
266
Abstract :
For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of >5.0. The MOM unit capacitance of 3.5 fF/um2 is achieved with only 4 metal layers.
Keywords :
CMOS integrated circuits; SRAM chips; low-power electronics; system-on-chip; CMOS process; SRAM chips; low standby transistors; memory size 2 MByte; size 32 nm; system-on-chip; voltage 1.1 V; CMOS technology; Capacitance; Foundries; MOS devices; Message-oriented middleware; Power transistors; Radio frequency; Random access memory; Testing; Varactors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
Type :
conf
DOI :
10.1109/IEDM.2007.4418918
Filename :
4418918
Link To Document :
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