Title :
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell
Author :
Fenouillet-Beranger, C. ; Denorme, S. ; Icard, B. ; Boeuf, F. ; Coignus, J. ; Faynot, O. ; Brevard, L. ; Buj, Christel ; Soonekindt, Christophe ; Todeschini, J. ; Le-Denmat, J.C. ; Loubet, N. ; Gallon, C. ; Perreau, P. ; Manakli, S. ; Mmghetti, B. ; Pain,
Author_Institution :
STMicroelectronics, Crolles
Abstract :
In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good Ion/Ioff performance for nMOS and pMOS transistors in the ultra-low-leakage regime (Ioff=6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/Vdd 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm2 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.
Keywords :
SRAM chips; high-k dielectric thin films; integrated circuit design; logic design; power MOSFET; silicon-on-insulator; LOP nodes; LSTP nodes; SRAM bitcell; fully-depleted SOI technology; high-k single-metal gate; nMOS transistors; pMOS transistors; size 32 nm; Boats; Capacitance; Electrodes; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; MOSFETs; Thin films; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418919
