Title :
Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications
Author :
Ko, C.H. ; Ge, C.H. ; Chen, C.C. ; Teo, W.Y. ; Lin, H.N. ; Chen, H.W. ; Kuo, C.W. ; Yang, M.T. ; Chen, D.Y. ; Fu, C.Y. ; Lee, W.C.
Author_Institution :
Taiwan Semicond. Manuf. Co. Ltd., Hsinchu
Abstract :
The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed improvement. When combined with high-stress contact-etch-stop-layer (CESL) , a significant 27% CMOS enhancement is achieved through preferable strain superposition. Both device integrity and reliability are carefully evaluated and neither of them is adversely impacted by DTE.
Keywords :
CMOS integrated circuits; nanoelectronics; CESL scheme; DTE; NMOS enhancement; PMOS enhancement; contact-etch-stop-layer scheme; diffusion topography engineering; high performance CMOS applications; CMOS process; Capacitive sensors; Compressive stress; MOS devices; Performance gain; Reliability engineering; Semiconductor device manufacture; Substrates; Surface topography; Thermal stresses;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418921
