Title :
Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations
Author :
Goh, Patrick ; Schutt-Ainé, José E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign Urbana, Urbana, IL, USA
Abstract :
In this paper, we present an application of the latency insertion method (LIM) to the transient simulations of CMOS circuits and compare it to traditional SPICE based methods. In addition, we extend the multi-rate simulation technique and apply it to the simulation of CMOS circuits in the LIM environment and illustrate its computational efficiently over the basic LIM.
Keywords :
CMOS integrated circuits; SPICE; integrated circuit modelling; CMOS circuit simulations; SPICE; computational efficiently; latency insertion method; multi rate considerations; multi rate simulation; transient simulations; Adders; CMOS integrated circuits; Computational modeling; Integrated circuit modeling; Numerical models; SPICE; Semiconductor device modeling; CMOS; circuit simulation; latency insertion method (LIM); multi-rate simulation;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
DOI :
10.1109/EPEPS.2011.6100205
