Title :
High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster
Author :
Ohta, H. ; Tamura, N. ; Fukutome, H. ; Tajima, M. ; Okabe, K. ; Hatada, A. ; Ikeda, K. ; Ohkoshi, K. ; Mori, T. ; Sukegawa, K. ; Satoh, S. ; Sugii, T.
Author_Institution :
Fujitsu Lab. Ltd., Tokyo
Abstract :
A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesn´t require any additional capping layers used in SMT. DCL fabricated directly on the gate dielectric film effectively improved drive currents without degrading short channel immunity because DCL technique dose not affect halo, extension and source/drain (S/D) profiles. The higher dopant concentration in DCL resulted in both the better electron mobility and the thinner equivalent oxide thickness of inversion layer capacitance (Teff). Consequently, the higher drive currents of 1204 muA/mum and 786 muA/mum were obtained at Vdd=1.0 V for nMOSFET and pMOSFET, respectively.
Keywords :
MOSFET; dielectric thin films; electron mobility; inversion layers; stress effects; bulk CMOS; capping layers; dopant confinement layer technique; electron mobility; gate dielectric film; inversion layer capacitance; nMOSFET; pMOSFET; short channel immunity; size 40 nm; strain booster; stress memorization technique; voltage 1 V; CMOSFETs; Capacitive sensors; Electrodes; Etching; Lamination; MOS devices; MOSFET circuits; Silicon compounds; Stress; Surface-mount technology;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418925