45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application

Author

Fung, Samuel K H ; Lo, H.C. ; Cheng, C.F. ; Lu, W.Y. ; Wu, K.C. ; Chen, K.H. ; Lee, D.H. ; Liu, Y.H. ; Wu, I.L. ; Li, C.T. ; Wu, C.H. ; Hsiao, F.L. ; Chen, T.L. ; Lien, W.Y. ; Huang, C.H. ; Wang, P.W. ; Chiu, Y.H. ; Lin, L.T. ; Chen, K.Y. ; Tao, H.J. ; Tu

Author_Institution

Taiwan Semicond. Manuf. Co., Hsinchu

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

1035

Lastpage

1037

Abstract

45 nm SOI CMOS technology target for high performance CPU application is reported. Process induced strained CMOS demonstrates 1232/855 uA/um DC Ion at 100 nA/um Ioff under Vdd=lV, which is the highest ever reported performance at 45 nm ground rule for both SOI and bulk technology. Small width PFET reaches record high 975uA/um. High SiGe over Si volume ratio in thin film SOI enables high compressive stress even at small device width and active area. Hole mobility is enhanced by 3X and Ion is increased 2X. On top of record high drive current, asymmetric transistor is implemented to further improve energy-delay by 20%. Our 45 nm SOI technology offers industry leading performance in terms of speed, energy and density.

Keywords

CMOS integrated circuits; Ge-Si alloys; hole mobility; integrated circuit testing; nanotechnology; silicon-on-insulator; CMOS technology; PFET; SiGe; asymmetric transistor; compressive stress; energy-delay improvement; hole mobility enhancement; silicon-on-insulator; size 45 nm; Annealing; CMOS technology; Capacitive sensors; Germanium silicon alloys; MOSFETs; Random access memory; Semiconductor thin films; Silicon germanium; Stress; Surface-mount technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418928

Filename

4418928