Title :
System design considerations for a 5Gb/s source-synchronous link with common-mode clocking
Author :
Jihong Ren ; Dan Oh ; Kollipara, R. ; Qi Lin
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate -13dB mode conversion on both differential pairs at 5Gb/s.
Keywords :
clocks; electric impedance; integrated circuit design; bit rate 5 Gbit/s; clock distribution delays; clocking scheme; common mode clocking; differential data channels; differential signaling systems; impedance control; source synchronous signaling system; system design considerations; Clocks; Microstrip; Common mode clocking; Source synchronous; mode conversion;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
DOI :
10.1109/EPEPS.2011.6100210