Title :
Very Low Vt [Ir-Hf]/HfLaO CMOS Using Novel Self-Aligned Low Temperature Shallow Junctions
Author :
Cheng, C.F. ; Wu, Cathy H. ; Su, N.C. ; Wang, S.J. ; McAlister, S.P. ; Chin, Albert
Author_Institution :
Nat. Chiao-Tung Univ., Hsinchu
Abstract :
We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good Phim-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85degC BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Keywords :
MOSFET; VLSI; dielectric materials; dielectric thin films; electric potential; hafnium alloys; hafnium compounds; interface states; iridium alloys; semiconductor device models; semiconductor device reliability; semiconductor junctions; BTI reliability; CMOSFET process; IrHf-HfLaO; VLSI; electron volt energy 4.1 eV; highly-scaled equivalent oxide thickness; interfacial reactions; metal-gate-high-k CMOS; n-MOS; p-MOS; self-aligned low temperature shallow junctions; size 1.2 nm; temperature 85 C; time 1 h; voltage 0.03 V; voltage 0.05 V; CMOS process; Capacitance-voltage characteristics; Channel bank filters; Hafnium compounds; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Implants; Microelectronics; Temperature dependence;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418939
